VHDL:Modular Design and Synthesis of Cores and Systems

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Considered and industry classis, VHDL:Modular Design and Synthesis of Cores and Systems has been fully updated to cover methodologies of modern design and the latest uses of VHDL for digital system design. You'll learn how to utilize VHDL to create specific constructs for specific hardware parts, focusing on VHDL's new libraries and packages. The cutting-edge resource explores the design of RT level components, the application of these components in a core-based, and the development of a complete processor design with its hardware and software as a core in a system-on-a-chip(SOC). Filled with over 150 illustrations, VHDL:Modular Design and Synthesis of Cores and Systems features: An entire toolkit for register-transfer level digital system design Testbench development techniques New to this edition: Coverage of the latest uses of VHDL for digital system design, design of IP cores, interactive and self-checking testbench development, and VHDL's new libraries and packages Inside this State-of-the-Art VHDL Design Tool Design Methodology VHDL Overview Structure of VHDL Simulation Model Combinational Circuits Sequential Circuits Testbench Development Control-Data Partitioned Designs Design of RTL Embedded Cores CPU RT Level Design CPU Memory Indtruction Level Testing Software Tools Embedded System Design About The Author Zainalabedin Navabi Ph.D., is professor of electrical and computer engineering at Northeastern University. Since 1981, he has been worked in the design, definition and implementation of Hardware Description Languages and synthesis and testing of digital systems. Dr. Navabi is an active member of IEEE DASC committee that sets standards related to hardware description languages. He is also the author of Verilog System Design and Embedded Core Design with FPGAs. Table Of Contents Preface Introduction Acknowledgments Chapter 1: Digital System Design Automation with VHDL Chapter 2: RTL with VHDL Chapter 3: VHDL Constructs for Structure and Hierarchy Descriptions Chapter 4: Concurrent Constructs for RT Level Descriptions Chapter 5: Sequential Constructs for RT Level Descriptions Chapter 6: VHDL Language Utilities and Packages Chapter 7: VHDL Signal Model Chapter 8: Hardware Cores and Models Chapter 9: Core Design and Testability Chapter 10: Design, Test and Application of a Processor Core APPENDIX A: VHDL KEYWORDS APPENDIX B: VHDL LANGUAGE GRAMMAR APPENDIX C: VHDLSTANDARD PACKAGES APPENDIX D: STD_LOGIC_1164 Package APPENDIX E: STD_LOGIC_TEXTIO Package APPENDIX F: STD_LOGIC_ARITH Package APPENDIX G: STD_LOGIC_SIGNED APPENDIX H: STD_LOGIC_UNSIGNED APPENDIX I: math_real Package INDEX