Functional Verification Of Programmable Embedded Architectures: A Top-Down Approach

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Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect's knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address twofundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems. Subjects of the book : Computer Science Contents of the book : PrefaceAcknowledgmentsI Introduction to Functional Verification1 Introduction1.1 Motivation1.1.1 Growth of Design Complexity1.1.2 Functional Verification - A Challenge1.2 Traditional Validation Flow1.3 Top-Down Validation Methodology1.4 Book OrganizationII Architecture Specification2 Architecture Specification2.1 Architecture Description Languages2.1.1 Behavioral ADLs2.1.2 Structural ADLs2.1.3 Mixed ADLs2.1.4 Partial ADLs2.2 ADLs and Other Specification Languages2.3 Specification Using EXPRESSION ADL2.3.1 Processor Specification2.3.2 Coprocessor Specification2.3.3 Memory Subsystem Specification2.4Chapter Summary3 Validation of Specification3.1 Validation of Static Behavior3.1.1 Graph-based Modeling of Pipelines3.1.2 Validation of Pipeline Specifications3.1.3 Experiments3.2 Validation of Dynamic Behavior3.2.1 FSM-based Modeling of Processor Pipelines3.2.2 Validation of Dynamic Properties3.2.3 A Case Study3.3 Related Work3.4 Chapter SummaryIII Top-Down Validation4 Executable Model Generation4.1 Survey of Contemporary Architectures4.1.1 Summary of Architectures Studied4.1.2 Similarities and Differences4.2 Functional Abstraction4.2.1 Structure of a Generic Processor4.2.2 Behavior of a Generic Processor4.2.3 Structure of a Generic Memory Subsystem4.2.4 Generic Controller4.2.5 Interrupts and Exceptions4.3 Reference Model Generation4.4 Related Work4.5 Chapter Summary5 Design Validation5.1 Property Checking using Symbolic Simulation5.2 Equivalence Checking5.3 Experiments5.3.1 Property Checking of a Memory Management Unit5.3.2 Equivalence Checking of the DLX Architecture5.4 Related Work5.5 Chapter Summary6 Functional Test Generation6.1 Test Generation using Model Checking6.1.1 Test Generation Methodology6.1.2 A Case Study6.2 Functional Coverage Driven Test Generation6.2.1 Functional Fault Models6.2.2 Functional Coverage Estimation6.2.3 Test Generation Techniques6.2.4 A Case Study6.3 Related Work6.4 Chapter SummaryIV Future Directions7 Conclusions7.1 Research Contributions7.2 Future DirectionsV AppendicesA. Survey of Contemporary ADLsA.1 Structural ADLsA.2 Behavioral ADLsA.3 Mixed ADLsA.4 Partial ADLsB. Specification of DLX ProcessorC. Interrupts & Exceptions in ADLD. Validation of DLX SpecificationE. Design Space ExplorationE.1 Simulator Generation and ExplorationE.2 Hardware Generation and ExplorationReferencesIndex