Computer Organization and Architecture: Designing for Performance

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Four-time winner of the best Computer Science and Engineering textbook of the year award from the Textbook and Academic Authors Association, Computer Organization and Architecture: Designing for Performance provides a thorough discussion of the fundamentals of computer organization and architecture, covering not just processor design, but memory, I/O, and parallel systems. Coverage is supported by a wealth of concrete examples emphasizing modern RISC, CISC, and superscalar systems. The eighth revision has been updated to reflect major advances in computer technology, including multicore processors and embedded processors. Interactive simulations have been expanded and keyed into relevant sections of text. Salient Features Multiple Perspectives: Systems are viewed from both the architectural (attributes of a system visible to a machine language programmer) and organizational (operational units and their interconnections that realize the architecture) perspectives to give students context. Unified Treatment of I/O: Provides full understanding of I/O functions and structures, including two important external interface examples: FireWire and InfiniBand. Focus on RISC: Students gain a broad understanding of this technology, found in virtually all contemporary machines. Parallel Processors: Exceptionally clear, well-organized treatment of symmetric multiprocessors (SMP), clusters, and NUMA systems. Running Case Studies: Case studies of Intel x86 and embedded ARM architectures supplement and explain material. Microprogrammed Implementation: This technology is given a full treatment, so students gain a complete understanding of processor organization. Table of Contents Chapter 1 Introduction Chapter 2 Computer Evolution and Performance Chapter 3 A Top-Level View of Computer Function and Interconnection Chapter 4 Cache Memory Chapter 5 Internal Memory Technology Chapter 6 External Memory Chapter 7 Input/Output Chapter 8 Operating System Support Chapter 9 Computer Arithmetic Chapter 10 Instruction Sets: Characteristics and Functions Chapter 11 Instruction Sets: Addressing Modes and Formats Chapter 12 Processor Structure and Function Chapter 13 Reduced Instruction Set Computers (RISCs) Chapter 14 Instruction-Level Parallelism and Superscalar Processors Chapter 15 Control Unit Operation Chapter 16 Microprogrammed Control Chapter 17 Parallel Processing1 Chapter 18 Multicore Computers Chapter 19 Number Systems Chapter 20 Digital Logic Chapter 21 The IA-64 Architecture Online Appendices Appendix C Hash Tables Appendix D Victim Cache Strategis Appendix E Interleaved Memory Appendix F International Reference Alphabet Appendix G Virtual Memory Page Replacement Algorithms